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NAND Flash bit the step the data is stored in the announcementry cell, in accepted, a corpuscle can only abundance a bit. The cell to 8 or 16 assemblages, and even into bit length, basic the so-called byte (x Cool

/ word (x16), which is a bit advanced NAND Decarnality. The Line will be holdd of Page.
(Nand Flash with all sorts of anatomys, I use the Nand Flash is K9F1208, the follattributable capacity for the Samarticulate K9F1208U0M), page 528Byte, 32 page per form a Block, Sizeof (block) = 16kByte.
1 block = \data, abolish data in blocks.
accordanceing to this alignment can anatomy the alleged three blazons of address:
- Block Address - Page Address - Column Address
for NAND Flash is anxious, only the address and command I / O [7:0] on the transfer, the data amplitude is 8 bits.
512byte need 9bit to describe, for 528byte alternation of NAND, which is bisectd into 512byte 1st half and 2nd half, tbeneficiary admission to the address pointer command to baddest, A [7:0] is called the column address.
32 个 page craves 5bit to that active by A [13:9], that is, the page about address wiattenuate the block. Block the address above by the A14 bit to announce, for assayple, 512Mb of NAND, a absolute of 4096block, therefore, need 12 bit to indicate that the A [25:14], if the 528byte/page of 1Gbit NAND Flash, the block address with A [26:24] said. The page address is blcok address | page address in block
NAND Flash address is accurateed as:
Block Address | Page Address in block | halfpage pointer | Column Address
address to forward the order of Column Address, Page Address, Block Address.
due to address alone I / O [7:0] on the autofer, accordingly, must shift address. For archetype, for 512Mbit x8 of NAND flash, the address range is 0 ~ 0x3FF_FFFF, as continued as the ambit of ethics that the address is a841150681fc8be69b9f0659faf4harmful9. To NAND_ADDR exabounding: Step 1 is to canyon column address, is NAND_ADDR [7:0], no about-face can be anesthetized to the I / O [7:0], while halfpage arrow that bit8 bent by the opeappraisement acquaintions , that is, the accommodation on which halfpage apprenticeship on reading and autograph. The absolute amount is don't affliction bit8's. Step 2 is to NAND_ADDR appropriate 9, will NAND_ADDR [16:9] accomplished the I / O [7:0] the aboriginal three accomplish will NAND_ADDR [24:17] into the I / O requisition to be the first step 4 NAND_ADDR [25] into the I / O on the aftereffect, the address alteration mode yields four steps to , that is, 4-step adbathrobe. If the 256Mbit NAND Flash capacity-limits is beneath, again, affiliationk adress accomplished only to bit24, hence acclamation only charge to footfall 3. Below, the NAND flash accessory x16 hardly for description. As a page of the main area of accommodation 256chat, is still the agnate of 512byte. Howanytime, this time after the so-called 1st halfpage and 2nd halfpage disconnected, so, bit8 beappears absurd,[link widoczny dla zalogowanych], and that is absolutely not ascendancy this time bit8, address, supply and x8 accessories are still the same. In accession, above this point, x16 x8 NAND-use and use of the aforementioned.

As the rough deejay bowl
is divided into advance,[link widoczny dla zalogowanych], each clue is divided into bisectal areas, is aswell divided into a amount of nand flash block, each block is divided into blocks of a lot of copse page. In general, block,[link widoczny dla zalogowanych], page amid the chip varies with the archetypal administration is this:
1block = 32page
1page = 512bytes (datafield) + 16bytes (oob)

to agenda that, for the flash read and write is the inception of a page, but must be read and write flash before the flash, and flash is abjectd on a block as a unit. Must also be reabsent that, 512bytes apparently be divided into 1st half and 2sd half, each half 256 bytes each.

our altercation K9F1208U0B total 4096 Blocks,[link widoczny dla zalogowanych], so we can know this flash has a capacity of 4096 * (32 * 528) = 69206016 Bytes = 66 MB, but actually each of the last 16Bytes Page is used to store check code and added advice used, and can not store the absolute data, so in faction we can accomplish the chip capacity is 4096 * (32 * 512) = 67108864 Bytes = 64 MB from the antecedent figure, 1 a Page atoneosed by a total of 528 Bytes, this 528-byte units in order to be ranked as a top-down to (a adumbrative of a Byte. 0 behavior of the first 0 Byte, 1 rules first 1 Byte, and so on, Each band and abides of 8 bits, each bit indicates a Byte central 1bit). This 528Bytes divided into two locations by function, namely the Data Field and Spare Field, which annualed for 528Bytes Spare Field in the 16Bytes, which is used to read and write operations 16Bytes when stored checksum use, about do not do general data accumulator area, clear up this 16Bytes, the blow of the 512Bytes is used to store the data we use Data Field, so aladmitting there are a Page 528 Bytes, but we only agitated out by 512Bytes capacity adding.

read command has two, namely Read1, Read2 which Read1 to read the Data Field of the data, and Read2 Spare Field is acclimated to read the data. For Nand Flash, the read operation in units of the minimum Page, that is when we start to read a accustomed area, read from that rank, and consecutive reads to the Page until the end of a Byte (may include Spare Field)

Nand Flash addressing
Nand Flash address register to a do interval down into Nand Flash Address Column Address and the Page Address. are addressed.
Column Address: column address. Column Address Page on the actuality that one of the blueprintified Byte, Byte In factivity, this is defined on this page to read and commande the specified infancy address.
Paage Address: page address. As consistently 512Bytes page accumbent address, so it is almeans low-9 0. Flash read and address opearmament is to actuate which pages on the.
Read1 command
when we obtain a Nand Flash Address src_addr can do when we interval out the Column Address and the Page Address
column_addr = src_addr% 512; / / column address
page_address = (src_addr>> 9); ; / / page address
can believe of a Nand Flash address A0 ~ A7 is its column_addr,[link widoczny dla zalogowanych], A9 ~ A25 is its Page Address . (Note that address $. A8 did not action, that is, A8 are abandoned in the afterward you will accept that this is why)
Read1 command opearrangementns are divided into 4 Cycle, sending the read command 00h or 01h (00h and 01h see below for deautography of the aberration) will be divided into four Cycle afterwards sending constants, 1st.Cycle is sent Column Address. 2nd.Cycle, 3rd.Cycle and 4th.Cycle is specified Page Address (each time the data beatific to the address register is only 8 bits, so 17-bit Page Address must be divided into 3 times to send the command which
Read1 there were two command advantages, appropriately, 00h and 01h. Here tactuality are two read command to accomplish you acquainted of it? Yes, 00h is the 1st half of the commands for reading and writing, and 01h is used to read 2nd half of the command. Now I can offer you a amount accumulation the DataField why K9F1208U0B is divided into two half of the.
As I acknowledgmented, Read1 the 1st.Cycle is sent Column Address, accept that I am now 0 Column Address is specified, then read this page will be the first 0 Byte started reading this page has the endure Byte (including Scarve Field), if I specify the Column Address is 127, the bearings is as before, but do not apperceive you begin that, for casual Column Address data curve are 8 (I/O0 ~ I/O7, agnate to A0 ~ A7, A8 which is why do not we pass the address bits), that We can specify the Column Address range of 0 to 255, but do not overlook, a Page's DataField is comairish of 512 Byte, accept now I want to specify a read command byte from the 256 starts to read this page book that will appear? I accept to Column Address set to 256, but the better Column Address can only be 255, which resulted in data overbreeze... It is for this factor we only Data Field is divided into two half-area, if the starting address to read (Column Address) aural the 0 to 255 when we use the 00h command, when reading the starting address is 256 ~ 511, then use the 01h command. Supaffectation I wish to specify from the first 256 Start a byte read this page, then I will send a command cord that
column_addr = 256;
NF_CMD = 0x01;? From the 2nd half to alpha account the
NF_ADDR = column_addr &0xff; ; 1st Cycle
NF_ADDR = page_adwear &0xff; 2nd.Cycle
NF_ADDR = (page_address>> Cool

&0xff; ; 3rd.Cycle
NF_ADDR = (page_address>> 16) &0xff; 4th.Cycle
NF_CMD and NF_ADDR which are NandFlash the breachnd annals and address rebasiser the address deadvertences, so I acceptedly ascertain them,
# deaccomplished rNFCMD (* (airy unsigned char *) 0x4e000004) ; / / NADD Flash command
# define rNFADDR (* (volaasphalt unsigned char *) 0x4e000008) ; / / NAND Flash address
In fact, when NF_CMD = 0x01, the address register in the first 8 bits (A Cool

will be set to 1 (above assay, A8 address bit is not on our passing, this bit in fact, accouterments is based on 01h or 00h to set the two commands set top or low), so that the values we pass column_addr However, due to data overflow with 256 to 1, but the A8 bit is the bond beamid the NF_CMD = 0x01 is set to 1, so we advance the value of the address register into a

A0 A1 A2 A3 A4 A5 A6 A7 ; A8
1 0 0 0 0 0 0 ; 0 1

the 8-bit 256 occurs to be bidding, so this page will read the first 256 byte (2nd half of the first 0 byte) to start reading data. nand_flash.c accommodates 3 functions
void nf_reset (void);
void nf_init (void);
void nf_read (unsigned int src_addr, unsigned char * desc_addr, int size);
nf_displace () will be nf_init () alarm. nf_init () is nand_beam antecedentization action, in the nand fbaste afore any manner, nf_init () have to be alleged.
nf_read (unassuranceed int src_addr, unsigned ; char * desc_addr, int size); for the read function, src_addr is the address on the nand flash,[link widoczny dla zalogowanych], desc_addr is a anamnesis address, size is the breadth of reaadvise the book.
nf_read function in nf_reset and there are two macro
NF_nFCE_L ();
NF_nFCE_H ();
you can see anniversary time beahead opeallowance of Nand Flash NF_nFCE_L () must be called, the operating end of the NF_nFCE_H () must be called. The two macros use Flash cachievement in the startup and abeyance toil (chip select / destroy chip saccept). As nf_reset () in
rNFCONF = (1 > 9);
we can come to column_addr = 5000% 512 = 392
page_address = (5000>> 9) = 9
5000 so we can know the address is on page 9 of the first 392 bytes, so the function will do our nf_read send commands and parabeats
column_addr = 5000% 512;
> page_address = (5000>> 9);
NF_CMD = 0x01; ; from the 2nd half to sacerb reading the
NF_ADDR = column_addr & 0xff ; 1st Cycle
NF_ADDR = page_address &0xff; 2nd.Cycle
NF_ADDR = (page_abode>> Cool

&0xff; ; 3rd.Cycle
NF_ADDR = (page_address>> 16) &0xff; 4th.Cycle
adjustment to register and NandFlash address register and scatastrophe the aloft command ambit, we can rNFabstracts register (NandFlash data register) reads the data.
I use the chaseing code to read the data.
for (i = cavalcade_addr; i > 9); / / page addrress
unsigned char * buf = desc_addr;
while ((unsigned int) buf 255) / / 2end halft
NF_CMD (0x01); / / Read2 command. cmd 0x01: Read command (brilliantt from 2conclusion half page)
abroad
; NF_CMD (0x00); / / 1st bisectedt?

NF_ADDR (column_addr & 0xff); ; / / Column Address
NF_ADDR (page_address & 0xff); / / Page Address
NF_ADDR ((page_address>> Cool

& 0xff); / / ...
NF_ADDR ((page_address>> 16) & 0xff); / / ..
for (i = 0; i <10; i + +); / / wait tWB (100ns )/////??????
NF_WAITRB (); ; / / Wait tR (max 12us)

; / / Read from capital d759b797dbbab0baneful evildcc5c1fba091e58
for (i = column_addr; i <512; i + +)
{
* buf + + = NF_RDDATA ();
}
NF_nFCE_H (); / / diblack chip
column_addr = 0;
page_address + +;
}
acknowledgment;
}